Anup Kumar Das Author & Editor

Anup Kumar Das is an Assistant Professor at Drexel University. He received a Ph.D. in Embedded Systems from National University of Singapore in 2014. Prior to his Ph.D., he was a research engineer for more than 7 years at ST Microelectronics (India and Grenoble) and LSI Corporation (India). Following his Ph.D., he was a post-doctoral fellow at the University of Southampton from 2014 to 2015 and a researcher at IMEC from 2015 to 2017. His research focuses on neuromorphic computing, from algorithm development to architectural exploration.  His other research interests include System-level design techniques for lifetime and energy optimization, Soft-error tolerance of FPGA configuration bitstream, Synchronous data flow graph based task mapping and scheduling, Probabilistic energy and performance optimization of multiprocessor systems, architectural adaptations for lifetime improvement of multiprocessor, and Design-for-testability (DFT) of multi-power domain SoC.

Akash Kumar is a Professor at TU Dresden.  He received the B.Eng. degree in computer engineering from the National University of Singapore (NUS), Singapore, in 2002, the joint Master of Technological Design degree in embedded systems from NUS and the Eindhoven University of Technology (TUe), Eindhoven, The Netherlands, in 2004, and the joint Ph.D. degree in electrical engineering in the area of embedded systems from TUe and NUS, in 2009. His specialities include multiprocessor architectural design, synchronous dataflow graphs, FPGA tool flows and Xilinx FPGA boards.

Bharadwaj Veeravalli, Member, IEEE & IEEE-CS, received his BSc in Physics, from Madurai-Kamaraj University, India in 1987, Master's in Electrical Communication Engineering from Indian Institute of Science, Bangalore, India in 1991 and PhD from Department of Aerospace Engineering, Indian Institute of Science, Bangalore, India in 1994. He received Gold Medals for his Bachelor's Degree overall performance and for an outstanding PhD thesis (Sabitha Chowdhary Gold Medal, IISc, Bangalore India) in the years 1987 and 1994, respectively.. He did his post-doctoral research in the Department of Computer Science, Concordia University, Montreal, Canada, in 1996. He is currently with the Department of Electrical and Computer Engineering, Communications and Information Engineering (CIE) division, at The National University of Singapore, Singapore, as a tenured Associate Professor. His main stream research interests include, Cloud/Grid/Cluster Computing, Scheduling in Parallel and Distributed Systems, Bioinformatics & Computational Biology, and Multimedia Computing. He is one of the earliest researchers in the field of Divisible Load Theory (DLT). He had successfully secured several externally funded projects. He has published over 100 papers in high-quality International Journals and Conferences. He has co-authored three research monographs in the areas of PDS, Distributed Databases (Competitive Algorithms), and Networked Multimedia Systems, in the years 1996, 2003, and 2005, respectively. He had guest edited a special issue on Cluster/Grid Computing for IJCA, USA journal in 2004. He is currently serving the Editorial Board of IEEE Transactions on Computers, IEEE Transactions on SMC-A, Multimedia Tools & Applications (MTAP) and Cluster Computing, as an Associate Editor. He was a Visiting Professor with HUST, Wuhan, China, from June 2007-May 2009. He had served (and serving) as a program committee member and as a Session Chair in several International Conferences. In September 2010, he has been invited to deliver keynote speech in fifth IEEE International Conference on Bio-Inspired Computing: Theory and Applications (BIC-TA) September 2010, held in Changsha, PR China 

Francky Catthoor received a Ph.D. in El. Eng. from the K.U.Leuven, Belgium in 1987. Since then, he has headed several research domains in the area of architectural methodologies and system synthesis for embedded multimedia and telecom applications, all within the DESICS division at IMEC, Leuven, Belgium. His current research activities mainly belong to the field of system-level exploration, with emphasis on data storage/transfer and concurrency exploitation, both in customized and programmable (parallel) instruction-set processors.