Reconfigurable and Adaptive Computing

This book presents innovative research on hardware architecture, focusing on reconfigurable and adaptive computing systems, including practical applications and advanced methodologies.

This book delves into the latest advancements in hardware architecture, focusing on reconfigurable and adaptive computing systems. It provides practical solutions to contemporary challenges in computer and network security, next-generation sequencing, and more. The text also covers enhanced methods for video watermarking, routing, and overall system performance, making it a valuable resource for professionals in the field.

Reconfigurable and Adaptive Computing highlights the potential of reconfigurable computing techniques and adaptive systems as leading architectures for microprocessors. The initial section of the book discusses reconfigurable systems, featuring a software and hardware co-design flow tailored for coarse-grained systems-on-chip. It introduces a video watermarking algorithm designed for the H.264 standard, presents solutions for regular expression matching systems, and showcases a novel FPGA-based acceleration solution integrated with the MapReduce framework across multiple hardware accelerators.

The subsequent section shifts focus to network-on-chip, detailing an implementation of a multiprocessor system-on-chip platform that allows shared memory access. Additionally, it models end-to-end quality-of-service metrics in a multi-application environment and introduces a 3D ant colony routing (3D-ACR) approach with three distinct 3D topologies. The final section explores the methodology of system co-design, proposing a new software-hardware co-design flow for embedded systems that treats both processors and intellectual property cores as services, along with an efficient algorithm for dependent task co-design using the greedy partitioning and insert scheduling method (GPISM).